Application Note
《Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design Guidelines》
4.5 Simulation Integrity Analysis 信号完整性分析
The general methodology for evaluating signal integrity for high-speed SERDES interfaces is illustrated in Figure 4-2.
评估高速SERDES接口信号完整性的一般方法如图4-2所示。
This involves running a channel simulation for the serial link.
这涉及到为串行链路运行信道模拟。
The methodology uses IBIS-AMI (Algorithmic Modeling Interface) models for the Tx/Rx blocks.
该方法为Tx/Rx块使用IBIS-AMI（算法建模接口）模型。
The basic setup and settings documented here can be used to validate all SerDes links and also across a variety of EDA Signal Integrity simulators.
这里记录的基本设置和设置可用于验证所有SerDes链路，也可用于验证各种EDA信号完整性模拟器.
This channel simulation should be performed as a signoff check for all high-speed Serial Link interfaces.
该信道模拟应该作为所有高速串行链路接口的验收检查来执行。
Figure 4-2. Signal Integrity Analysis Setup - Channel Simulation
4.5.1 Simulator Settings and Model Usage仿真设置和模型使用
The following things need to be kept in mind while performing channel simulation:
在进行通道模拟时需要牢记以下事项：
• Odd mode crosstalk is used to define aggressor and victim switching in opposite directions. This is required if multiple lanes are simulated.
奇模串扰指干扰信号与受扰信号反向传输的场景。在仿真多通道系统时，必须考虑该模式。
• An important note to keep in mind is that the jitter and noise of Tx/Rx blocks should not be double counted.
要记住的一个重要注意事项是，Tx/Rx块的抖动和噪声不应该被重复计算。
As the IBIS-AMI models already have the various jitter sources incorporated, the option to include additional jitter in these blocks must be turned off in the EDA simulation engine of choice.
由于IBIS-AMI模型已经包含了各种抖动源，因此必须在EDA仿真引擎中关闭在这些块中包含额外抖动的选项。
4.5.2 Simulation Parameters仿真参数
The serial link simulations involve a parametric sweep:
串行链路仿真涉及参数扫描：
• Corners: The IBIS-AMI models for Tx/Rx are characterized as Fast/Typ/Slow corners. The different Deterministic and Random Jitter budgets are built in to the models using these corners.
弯道：用于Tx/Rx的IBIS-AMI模型的特点是快速/快速/慢速弯道。不同的确定性和随机抖动预算使用这些角构建到模型中。
• Transmitter Presets: These are specific to each standard and control the coefficients in the transmitter DFE (Decision Feedback Equalizer).
发射器预设：这些是特定于每个标准的，并控制发射器DFE（决策反馈均衡器）中的系数。
These presets also model the level of de-emphasis in the transmit amplifier which are required to equalize the overall system-level response across different frequencies and counteract the impact of ISI (Inter-symbol interference).
这些预设还模拟了发射放大器的去加重水平，这是平衡不同频率的整体系统级响应和抵消ISI（符号间干扰）影响所必需的。
It is recommended using a parametric sweep and simulate for all different transmitter presets for a given Serial Link protocol.
建议对给定串行链路协议的所有不同的发送器预设使用参数扫描和仿真。
This is due to the fact that the best eye observed can be highly dependent on the system impulse response and therefore different presets could yield the best results on different systems.
这是由于观察到的最佳眼图可能高度依赖于系统脉冲响应，因此不同的预设可以在不同的系统上产生最佳结果。
• Data Patterns: It is recommended to use PRBS23 or PRBS31 patterns to validate the system, in order to excite larger levels of ISI.
数据模式：建议使用PRBS23或PRBS31模式来验证系统，以便激发更大级别的ISI。
4.5.3 Simulation Methodology仿真的方法
For interfaces where the eye mask is specified in terms of a BER target it is recommended to run the initial channel simulations for around 100K bits and observe the extrapolated bathtub curves for the corresponding target BER, as reported by the simulator.
对于眼罩以误码率目标指定的接口，建议运行大约100K bits的初始信道仿真，并观察由仿真器报告的相应目标误码率的外推浴盆曲线。
Another simulation for around 500K and 1M bits can be rerun and the bathtub curves can be overlaid to observe the impact of running for larger bit sequences.
可以重新运行约500K和1M bits的另一个仿真，并且可以覆盖浴盆曲线，以观察运行更大位序列的影响。
An example of voltage bathtub curves overlaid is shown in Figure 4-3. Similar overlay can be made for the jitter bathtub curves.
电压浴盆曲线叠加示例如图4-3所示。类似的覆盖可以为抖动浴盆曲线。
Typically, all the ISI should be accounted for within the first 100K bits of the simulation and beyond this point, all bathtub curves should converge if the Random Jitter (Rj) in the models is sufficiently small.
通常情况下，所有ISI都应该在仿真的前100K bits内考虑，超过这一点，如果模型中的随机抖动（
Rj）足够小，所有浴盆曲线都应该收敛。
It is recommended to confirm this convergence up front by running at least one set of system-level channel simulations each for 100K, 500K and 1M bit sequences.
建议通过对100K、500K和1M bits顺序分别运行至少一组系统级通道仿真来确认这种收敛性。
If the voltage and jitter bathtub curves from each of these simulations are almost identical, the remainder of the simulations can be run at 100K bits to optimize run times.
如果这些仿真的电压和抖动浴盆曲线几乎相同，则可以在100K bits上运行其余的仿真以优化运行时间。
For interfaces where the eye mask is not specified for any particular BER target, a 100K bit simulation should suffice.
对于没有为任何特定误码率目标指定眼罩的接口，100K bits的仿真应该足够了。