后端设计笔记11 EPS功耗分析

发布于：2025-06-30 ⋅ 阅读:(20) ⋅ 点赞:(0)

1.理论

 

flip chip 和wire bond封装不一样

亚阈值漏电   隧穿效应   反偏电流

一、动态功耗

动态功耗发生在电路状态切换过程中，占总功耗的主要部分（通常超过70%），可进一步分为两类：

  1. 开关功耗（翻转功耗）
    • 产生原因：逻辑门状态翻转时对负载电容充放电消耗的能量。例如，CMOS反相器输出从0→1时电源对负载电容充电，1→0时电容放电137。
    • 计算公式：Pswitch=α⋅CL⋅VDD2⋅fPswitch​=α⋅CL​⋅VDD2​⋅f
      • αα：活动因子（节点翻转概率）
      • CLCL​：负载电容（含连线电容、扇出电容等）
      • VDDVDD​：电源电压
      • ff：时钟频率459。
  2. 短路功耗（内部功耗）
    • 产生原因：输入信号跳变过程中，PMOS与NMOS短暂同时导通，形成电源到地的直流通路电流127。
    • 影响因素：输入信号边沿斜率（越缓慢则导通时间越长）、负载电容（负载电容大可缩短同时导通时间）59。

⚡️ 关键特性：动态功耗与 VDD2VDD2​ 和 ff 正相关，因此降低电压或频率可显著优化功耗58。

🔋 二、静态功耗

静态功耗指电路稳定无翻转时的功耗，主要由漏电流引起，在纳米级工艺中占比显著提升：

  1. 亚阈值漏电流
    • 晶体管未完全关断时，源漏极间因亚阈值导电效应产生的漏电流，随工艺尺寸缩小（阈值电压降低）而增大31013。
  2. 栅极漏电流
    • 栅氧层厚度减薄后，载流子隧穿栅介质形成的电流47。
  3. 反偏PN结漏电流
    • 源/漏扩散区与衬底间反偏二极管的泄漏电流，通常较小412。
  4. 竞争电流（特殊电路）
    • 非静态电路（如有比逻辑）在稳态时存在的直流通路电流5。

🌡️ 关键特性：静态功耗随温度升高指数级增长，且与工艺关联紧密（如高阈值器件可抑制漏电）1014。

这里的静态功耗分析和之前的静态功耗不是一个东西

 

输入信号的internal 查找表表示输入变化但是输出不变时的

输出变化的放在输出pin查找表里

功耗分析两种模式 net base  dmain ,考虑地抬效应

2.实践

1.tech lef需要写在所有lef的前面，这里只提取std的port view，所以只读lef

以下是脚本  static.libgen_std_fast.tcl

#######################################################
# EPS: generate power-grid libraries
# Run > eps -init script.tcl
#######################################################

#read_lib -lef 
source ../scripts/set_eps_libs.tcl
source ../scripts/set_global_vars.tcl

read_lib -lef $std_lefs

# fast library for all cells
set_power_library_mode \
-accuracy fast \
-celltype allcells \
-extraction_tech_file $pg_extraction_tech_file \
-lef_layermap $lef2tech_mapfile \
-generic_power_names {VDD 1.32} \
-generic_ground_names {VSS} \
-input_type pr_lef

characterize_power_library \
-filler_cells {SHFILL*} \
-decap_cells DCAP*  \
-output_directory ../power_grid_library/static/fast_allcells \
-celllist_file ../scripts/stdcell_list.txt \
-defaultcap 0.100

set_eps_ib



set std_lefs {
/disk2/course/library/stdcel/lef/saed90nm_tech.lef
/disk2/course/library/stdcel/lef/saed90nm_hvt.lef
/disk2/course/library/stdcel/lef/saed90nm.lef
/disk2/course/library/stdcel/lef/saed90nm_lvt.lef
}
set mem_lefs {
/disk2/course/library/stdcel/lef/saed90nm_tech.lef
/disk2/course/library/mem/lef/SRAM8x1024_1rw.lef
/disk2/course/library/mem/lef/SRAM8x128.lef
}
set eps_lib(lef) {
/disk2/course/library/stdcel/lef/saed90nm_tech.lef
/disk2/course/library/stdcel/lef/saed90nm_hvt.lef
/disk2/course/library/stdcel/lef/saed90nm.lef
/disk2/course/library/stdcel/lef/saed90nm_lvt.lef
/disk2/course/library/mem/lef/SRAM8x1024_1rw.lef
/disk2/course/library/mem/lef/SRAM8x128.lef
}

set eps_lib(ml_lib) {
/disk2/course/library/stdcel/lib/ff1p32v125c/saed90nm_min_ht_cg_hvt.lib
/disk2/course/library/stdcel/lib/ff1p32v125c/saed90nm_min_ht_cg.lib
/disk2/course/library/stdcel/lib/ff1p32v125c/saed90nm_min_ht_cg_lvt.lib
/disk2/course/library/stdcel/lib/ff1p32v125c/saed90nm_min_ht_hvt.lib
/disk2/course/library/stdcel/lib/ff1p32v125c/saed90nm_min_ht.lib
/disk2/course/library/stdcel/lib/ff1p32v125c/saed90nm_min_ht_lvt.lib
/disk2/course/library/mem/lib/ff1p32v125c/SRAM8x1024_1rw_min_ht_pg.lib
/disk2/course/library/mem/lib/ff1p32v125c/SRAM8x128_min_ht_pg.lib
}


set eps_lib(static_pgv) {
../power_grid_library/fast_allcells/fast_allcells.cl \
../power_grid_library/mem_detail/SRAM8x1024_1rw.cl \
../power_grid_library/mem_detail/SRAM8x128.cl \
}

set eps_lib(dynamic_pgv) {
../power_grid_library/static/fast_allcells/fast_allcells.cl
../power_grid_library/static/mem_detail/SRAM8x128.cl
../power_grid_library/static/mem_detail/SRAM8x1024_1rw.cl
}

set_global_vars.tcl


################ design ################
set design_top  	"oc8051_top"
set design_path 	"/disk2/course/proj/oc8051/09.Power_Analysis.oc8051/pnr/output_data/v0/"
set design_verilog     	"$design_path/${design_top}.output.all_for_eps.v"
set design_def 		"$design_path/${design_top}.output.filler.allvias.def"
set design_spef   	"$design_path/spef/cmax_125c.spef"
set design_sdc   	"/disk2/course/proj/oc8051/07.StarRC_STA_ECO/sta/cons/oc8051_func.sta.sdc"


################ tech ##################

set pg_extraction_tech_file "/disk2/course/proj/oc8051/09.Power_Analysis.oc8051/qrc_techfile/ict_to_qrc_NOMINAL/qrcTechFile"
set lef2tech_mapfile "../scripts/lefdef.layermap"
set gds_mapfile      "../scripts/gds.layermap"

此处只提取std的port view，所以只读lef

随后对mem进行detail_view抽取  ，static.libgen_mem_accuratee.tcl

#######################################################
# EPS: generate power-grid libraries
# Run > eps -init script.tcl
#######################################################

source ../scripts/set_eps_libs.tcl
source ../scripts/set_global_vars.tcl
read_lib -lef $mem_lefs

set_power_library_mode \
-accuracy accurate \
-celltype macros \
-extraction_tech_file $pg_extraction_tech_file \
-lef_layermap $lef2tech_mapfile \
-generic_power_names {VDD 1.32} \
-generic_ground_names {VSS} \
-input_type pr_lef

source ../scripts/mem_list.tcl
foreach MEM  $mem_list {
    echo "\n================> $MEM"
    echo $MEM > ./list/$MEM.list
    set gdsfile /disk2/course/library/mem/gds/${MEM}.gds
    set cdl /disk2/course/library/mem/cdl/${MEM}.cdl

    characterize_power_library \
    	-celllist_file ./list/${MEM}.list \
    	-spice_models ../../spice_models/models/SAED90nm.lib \
    	-spice_corners { FF_12 FF_12_hvt FF_12_lvt} \
    	-spice_subckts $cdl \
    	-gds_files $gdsfile \
    	-gds_layermap $gds_mapfile \
	-stop@via VIA1 \
    	-output_directory ../power_grid_library/static/mem_detail \
    	-assume_foreigns true \
    	-assume_foreigns_mode  1 
}

完成之后进入power_detaillib/static/mem_detail  路径

查看生成,过程中此error不用管

完成后开始做功耗分析  run_static_analyse.tcl


source ../scripts/set_global_vars.tcl

source ../scripts/set_eps_libs.tcl

source ../scripts/read_design.tcl

source ../scripts/static.power_calc.vector_less.tcl
#source ../scripts/static.power_calc.vector_based.tcl

source ../scripts/static.rail_analysis.tcl

read_design.tcl


set_multi_cpu_usage -localCpu 1
read_lib -lef $eps_lib(lef)

read_lib -max $eps_lib(ml_lib)

read_verilog $design_verilog

set_top_module $design_top

read_def $design_def


read_sdc $design_sdc

read_spef $design_spef



if {0} {
	verify_PG_short -net VDD
	verify_PG_short -net VSS
}

static.power_calc.vector_less.tcl


set_power_analysis_mode -reset
set_power_analysis_mode \
	-method static \
	-corner max \
	-create_binary_db true \
	-binary_db_name static.power.db \
	-write_static_currents true


set_default_switching_activity -reset
set_default_switching_activity \
	-input_activity 0.6 \
	-seq_activity 0.6
#set_switching_activity -inst 


if {0} {
set_default_switching_activity -reset
set_default_switching_activity -input_activity 0  -seq_activity 0

read_activity_file $vcd_file \
-format VCD \
-vcd_scope tb/TOP/u_Block1 \
-start 25000ns \
-end 26000ns
}

#set_power 15mw xxx
#set_multi_cpu_usage -localCpu 4

report_power -rail_analysis_format VS -outfile static.power.rpt

view_analysis_results -power_db static.power.db -plot ip
view_analysis_results -power_db static.power.db -plot ip_s
view_analysis_results -power_db static.power.db -plot ip_l
view_analysis_results -power_db static.power.db -plot freq
view_analysis_result  -power_db static.power.db -free_data

如果有vcd文件，使用以下脚本  static.power_calc.vector_based.tcl


set_power_analysis_mode -reset
set_power_analysis_mode \
	-method static \
	-corner max \
	-create_binary_db true \
	-binary_db_name static.power.db \
	-write_static_currents true


if {1} {
set_default_switching_activity -reset
set_default_switching_activity -input_activity 0  -seq_activity 0

read_activity_file $vcd_file \
-format VCD \
-vcd_scope tb/TOP/u_Block1 \
-start 25000ns \
-end 26000ns
}

#set_power 15mw xxx
#set_multi_cpu_usage -localCpu 4

report_power -rail_analysis_format VS -outfile static.power.rpt

view_analysis_results -power_db static.power.db -plot ip
view_analysis_results -power_db static.power.db -plot ip_s
view_analysis_results -power_db static.power.db -plot ip_l
view_analysis_results -power_db static.power.db -plot freq
view_analysis_result  -power_db static.power.db  -free_data

计算过程需要去掉在最后一行  -power_grid_library

完成可见打开报告gui

power&rail  >  power rail plots > 

打开界面后先set up db,填写db文件

随后选择需要查看的选项

如果看某一个特定原件的power，执行以下命令

接下来分析rail    static.rail_analysis.tcl


set_rail_analysis_mode -method static \
	-accuracy accurate \
 	-power_grid_library $eps_lib(static_pgv) \
 	-temp_directory_name ./tmpdir

set_power_data -reset
set_power_data -format current -scale 1 {static_VDD.ptiavg static_VSS.ptiavg }

set_power_pads -reset
set_power_pads -net VDD -format xy  -file ../scripts/vdd_pad.tmp.txt
#set_power_pads -net VDD -format xy  -file ../scripts/vdd_pad.txt
#set_power_pads -net VSS -format xy  -file ../scripts/vss_pad.txt

#set_power_pads -net VDD -format defpin
#set_power_pads -net VSS -format defpin

set_pg_nets -net VSS -voltage 0.0 -threshold 0.055 -tolerance 0.3
set_pg_nets -net VDD -voltage 1.32 -threshold 1.145 -tolerance 0.3

#set_rail_analysis_domain -name allDomains -pwrnets VDD  -gndnets VSS
#analyze_rail -type domain -results_directory ./ allDomains

analyze_rail -type net  -results_directory ./ VDD
analyze_rail -type net  -results_directory ./ VSS

通过set_power_pads可以设定power的pin,完成后生成VDD，fp pin一般来说是strap作为电源引脚

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