TC358774XBG/TC358775XBG
Mobile Peripheral Devices
Overview
The TC358774XBG/TC358775XBG Functional Specification defines
operation of the DSI SM to LVDS low power chip (or more abbreviated,
TC358775XBG chip). TC358775XBG is the follow-up chip of
TC358764XBG/ TC358765XBG, which:
1. Is pin compatible to TC358764XBG/TC358765XBG
2. Exhibit LVDS Tx block operates at 1.8V @135 MHz to reduce
operation power
3. Update 4-lane DSI Rx max bit rate @ 1 Gbps/lane to support
1920×1200×24 @60fps
4. Add STBY pin with to enable turning on VDDIO power first before
other power supplies.
The primary function of this chip is DSI-to-LVDS Bridge, enabling
video streaming output over DSI link to drive LVDS-compatible
display panels. The chip supports up to 1600×1200 24-bits per pixel resolution for single-link LVDS and
up to WUXGA (1920×1200 24-bits pixels) resolution for dual-link LVDS. As a secondary function, the
chip also supports an I 2 C Master which is controlled by the DSI link; this may be used as an interface to
any other control functions through I 2 C.
Features
● DSI Receiver
Configurable 1- up to 4-Data-Lane DSI Link with
bi-directional support on Data Lane 0
Maximum bit rate of 1 Gbps/lane
Video input data formats:
- RGB565 16-bits per pixel
- RGB666 18-bits per pixel
- RGB666 loosely packed 24-bits per pixel
- RGB888 24-bits per pixel
Video frame size:
- Up to 1600×1200 24-bits per pixel resolution to
single-link LVDS display panel, limited by 135
MHz LVDS speed
- Up to WUXGA resolutions (1920×1200 24-bits
pixels) to dual-link LVDS display panel, limited by
4 Gbps DSI link speed
Supports Video Stream packets for video data
transmission.
Supports generic long packets for accessing the
chip's register set
Supports the path for Host to control the on-chip
I 2 C Master
● LVDS FPD Link Transmitter
Supports single-link or dual-link
Maximum pixel clock frequency of 135 MHz.
Maximum pixel clock speed of 135 MHz for single
link or 270 MHz for dual-link
Supports display up to 1600×1200 24-bits per
pixel resolution for single-link, or up to 1920×1200
24-bits resolutions for dual-link
Supports the following pixel formats:
- RGB666 18-bits per pixel
- RGB888 24-bits per pixel
Features Toshiba Magic Square algorithm which
enables a RGB666 display panel to produce a
display quality almost equivalent to that of an
RGB888 24-bits panel
Flexible mapping of parallel data input bit ordering
Supports programmable clock polarity
Supports two power saving states
- Sleep state, when receiving DSI ULPS signaling
- Standby state, entered by STBY pin assertion
● System Operation
Host configures the chip through DSI link
Through DSI link, Host accesses the chip register
set using Generic Write and Read packets. One
Generic Long Write packet can write to multiple
contiguous register addresses
Includes an I 2 C Master function which is controlled
by Host through DSI link (multi-master is not
supported)
Power management features to save power
Configuration registers is also accessible through
I 2 C Slave interface
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