i.MX 6ULL 裸机 IAR 环境安装

一. IAR 的安装请自行搜索

二. 使用最新版本的 IAR，需要修改 SDK

1. 在 SDK 的 core_ca7.h 加上 

#include "intrinsics.h" /* IAR Intrinsics */ 

2. debug 时需要修改每个工程下的 ddr_init.jlinkscript，参考链接 

Solved: How to connect to imx6Ull with ddr_init.jlinkscript file? - NXP Community

/*********************************************************************
*              SEGGER MICROCONTROLLER GmbH & Co. K.G.                *
*        Solutions for real time microcontroller applications        *
**********************************************************************
*                                                                    *
*        (c) 2011-2015 SEGGER Microcontroller GmbH & Co. KG          *
*                                                                    *
* Internet: www.segger.com Support: support@segger.com               *
*                                                                    *
**********************************************************************
----------------------------------------------------------------------
Purpose : 
---------------------------END-OF-HEADER------------------------------
*/


void Clock_Init() {
  // Enable all clocks
  MEM_WriteU32(0x020c4068,0xffffffff);
  MEM_WriteU32(0x020c406c,0xffffffff);
  MEM_WriteU32(0x020c4070,0xffffffff);
  MEM_WriteU32(0x020c4074,0xffffffff);
  MEM_WriteU32(0x020c4078,0xffffffff);
  MEM_WriteU32(0x020c407c,0xffffffff);
  MEM_WriteU32(0x020c4080,0xffffffff);

  Report("Clock Init Done");
}

void DDR_Init() {
  // Config IOMUX for ddr
  MEM_WriteU32(0x020E04B4,0x000C0000);
  MEM_WriteU32(0x020E04AC,0x00000000);
  MEM_WriteU32(0x020E027C,0x00000030);
  MEM_WriteU32(0x020E0250,0x00000030);
  MEM_WriteU32(0x020E024C,0x00000030);
  MEM_WriteU32(0x020E0490,0x00000030);
  MEM_WriteU32(0x020E0288,0x00000030);
  MEM_WriteU32(0x020E0270,0x00000000);
  MEM_WriteU32(0x020E0260,0x00000030);
  MEM_WriteU32(0x020E0264,0x00000030);
  MEM_WriteU32(0x020E04A0,0x00000030);
  MEM_WriteU32(0x020E0494,0x00020000);
  MEM_WriteU32(0x020E0280,0x00000030);
  MEM_WriteU32(0x020E0284,0x00000030);
  MEM_WriteU32(0x020E04B0,0x00020000);
  MEM_WriteU32(0x020E0498,0x00000030);
  MEM_WriteU32(0x020E04A4,0x00000030);
  MEM_WriteU32(0x020E0244,0x00000030);
  MEM_WriteU32(0x020E0248,0x00000030);
  
  // Config DDR Controller Registers
  MEM_WriteU32(0x021B001C,0x00008000);
  MEM_WriteU32(0x021B0800,0xA1390003);
  MEM_WriteU32(0x021B080C,0x00150019);
  MEM_WriteU32(0x021B083C,0x41550153);
  MEM_WriteU32(0x021B0848,0x40403A3E);
  MEM_WriteU32(0x021B0850,0x40402F2A);
  MEM_WriteU32(0x021B081C,0x33333333);
  MEM_WriteU32(0x021B0820,0x33333333);
  MEM_WriteU32(0x021B082C,0xf3333333);
  MEM_WriteU32(0x021B0830,0xf3333333);
  MEM_WriteU32(0x021B08C0,0x00944009);
  MEM_WriteU32(0x021B08b8,0x00000800);

  // Config MMDC init
  MEM_WriteU32(0x021B0004,0x0002002D);
  MEM_WriteU32(0x021B0008,0x1B333030);
  MEM_WriteU32(0x021B000C,0x676B52F3);
  MEM_WriteU32(0x021B0010,0xB66D0B63);
  MEM_WriteU32(0x021B0014,0x01FF00DB);
  MEM_WriteU32(0x021B0018,0x00201740);
  MEM_WriteU32(0x021B001C,0x00008000);
  MEM_WriteU32(0x021B002C,0x000026D2);
  MEM_WriteU32(0x021B0030,0x006B1023);
  MEM_WriteU32(0x021B0040,0x0000005F);
  MEM_WriteU32(0x021B0000,0x85180000);
  MEM_WriteU32(0x021B0890,0x00400000);
  MEM_WriteU32(0x021B001C,0x02008032);
  MEM_WriteU32(0x021B001C,0x00008033);
  MEM_WriteU32(0x021B001C,0x00048031);
  MEM_WriteU32(0x021B001C,0x15208030);
  MEM_WriteU32(0x021B001C,0x04008040);
  MEM_WriteU32(0x021B0020,0x00000800);
  MEM_WriteU32(0x021B0818,0x00000227);
  MEM_WriteU32(0x021B0004,0x0002552D);
  MEM_WriteU32(0x021B0404,0x00011006);
  MEM_WriteU32(0x021B001C,0x00000000);

  Report("DDR Init Done");
}

/* ConfigTarget */
void ConfigTargetSettings(void)
{
  Report("J-Link script: Setting up AP map");

  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);

  CORESIGHT_AddAP(1, CORESIGHT_APB_AP);

  CORESIGHT_IndexAPBAPToUse = 1;
  Report("Config JTAG Speed to 4000kHz");
  JTAG_Speed = 4000;
}

/* SetupTarget */
void SetupTarget(void) {
  unsigned int reg;
  reg = MEM_ReadU32(0x021B0000);
  reg = reg & 0x80000000;

  if(reg == 0){
    Report("Enabling i.MX6ULL DDR3L");
    Clock_Init();
    DDR_Init();
  }
}