4-verilog简单状态机

verilog简单状态机

1.

always @ (posedge clk or negedge rst_n) begin
    if (!rst_n)
        cnt_1ms <= 20'b0;
    else 
        if (cnt_1ms_en)
            cnt_1ms <= cnt_1ms + 1'b1;
        else
            cnt_1ms <= 20'd0; 
end

always @ (posedge clk or negedge rst_n) begin
    if(!rst_n)
        cur_state <= s1_power_init;
    else if (EN_POWER_ON==1'b1)
		cur_state <= s1_power_init;
	else
        cur_state <= next_state;
end

always @ (*) begin
    case(cur_state)
        s1_power_init: begin                             // 初始化状态
            if (st_done==1'b1)
                next_state = s2_EN_12_power;
            else
                next_state = s1_power_init;
            end
        s2_EN_12_power: begin 
            if (st_done==1'b1)
                next_state = s3_EN_3_4_power;
            else
                next_state = s2_EN_12_power;
            end
        s3_EN_3_4_power: begin
            if (st_done==1'b1)
                next_state = s4_power_done;
            else
                next_state = s3_EN_3_4_power;
            end
        s4_power_done:begin
            if (st_done==1'b1)
                next_state = s5_reset_off;
            else
                next_state = s4_power_done;
            end  
        s5_reset_off:begin
            if (st_done==1'b1)
                next_state = s6_power_done;
            else
                next_state = s5_reset_off;
            end 
        s6_power_done:begin
            if (st_done==1'b1)
                next_state = s1_power_init;
            else
                next_state = s6_power_done;
            end        
        default: next_state = s1_power_init;
	endcase
end


always @ (posedge CLK_25M or negedge wLUTsLoad) begin
    if(!wLUTsLoad) begin
    end
    else begin
        st_done <= 1'b0;
        case (cur_state)
            s1_power_init:begin                              //初始化
                if(wEN_POWER_ON==1'b0)begin
                    cnt_1ms_en <= 1'b1;
                    if (cnt_1ms<10'd100)
                        st_done <= 1'b0;
                    else begin
                        st_done <= 1'b1;
						cnt_1ms_en <= 1'b0;
					end
                end
                else 
                    st_done <= 1'b0;
			end
            s2_EN_12_power:begin
                cnt_1ms_en <= 1'b1;
                if (cnt_1ms<10'd100)
                    st_done <= 1'b0;
                else begin
                    st_done <= 1'b1;
					cnt_1ms_en <= 1'b0;
				end
			end
            s3_EN_3_4_power:begin
                cnt_1ms_en <= 1'b1;
                if (cnt_1ms<10'd300)
                    st_done <= 1'b0;
                else begin
                    st_done <= 1'b1;
					cnt_1ms_en <= 1'b0;
				end
			end
            s4_power_done:begin
				if(PG_1V2&PG_1V8&PG_0V9&PG_3V3&PG_4V&PG_1V&PG_5V)begin
					cnt_1ms_en <= 1'b1;
					if (cnt_1ms<10'd100)
						st_done <= 1'b0;
					else begin
						st_done <= 1'b1;
						cnt_1ms_en <= 1'b0;
					end
				end
				else
					st_done <= 1'b0;
			end
			s5_reset_off:begin
				cnt_1ms_en <= 1'b1;
                if (cnt_1ms<10'd100)
                    st_done <= 1'b0;
                else begin
                    st_done <= 1'b1;
					cnt_1ms_en <= 1'b0;
				end
			end
			s6_power_done:begin
				if(EN_POWER_ON==1'b1) begin
					st_done <= 1'b1;
                end
				else begin
                    POWER_ON_OFF <= 1'b1;
					st_done <= 1'b0;
                end
			end
			default:;
		endcase	
	end
end